FPGA Guide
Topic hub

FPGA architecture

How an FPGA is built from the look-up table up to the die, and why the shape of the silicon decides what your design can do.

Updated 13 Nov 2026 · LUT, CLB, ALM, routing, block RAM, DSP slice, clock region, bitstream

Overview

An FPGA is a large array of small programmable logic cells, a programmable wiring network to join them, and a set of harder blocks (memory, multipliers, clock managers, transceivers) dropped into the array where the vendor thinks they will earn their area. This hub is for anyone who wants to understand what the synthesiser is actually targeting, so that the numbers in a utilisation report and the red paths in a timing report make sense.

The architecture matters because every design decision is a decision about silicon. A 64-bit adder costs a run of carry chain. A 2 KB lookup costs one block RAM, whether you use all of it or not. A clock that crosses the whole die costs a global buffer and some skew. Once you can see the fabric, you can predict cost before you build, and you can read a vendor datasheet without being misled by headline numbers.

Key ideas

The logic cell: LUT, flip-flop and carry

The LUT is a tiny memory. A 6-input LUT holds 64 bits and can implement any Boolean function of six inputs by storing its truth table. Next to it sits a flip-flop, so that the output can be registered, and a dedicated carry path so that adders and counters do not have to be built out of general LUTs. AMD groups eight such cells into a CLB slice pair. Altera calls its cell an adaptive logic module (ALM), which is a fracturable 8-input structure that can act as one large or two smaller LUTs. Lattice, Gowin and Efinix mostly use 4-input LUTs, which are smaller and cheaper but need more of them for the same function. Comparing “logic cells” across vendors is therefore approximate at best.

Switchmatrixprogrammablerouting muxesLogic tile (one slice of a CLB)LUT664-bit tableLUT664-bit tablecarry chainFFFFinputscout to tile abovecin from tile belowoutputs back into the routing networkclk
A simplified logic tile: two 6-input LUTs, a carry chain, flip-flops and the local interconnect that connects the tile to the switch matrix.

Routing and the bitstream

Most of the area and most of the delay in an FPGA is wiring, not logic. Every cell connects through programmable multiplexers to tracks of different lengths, and the placer and router spend their time picking which tracks to use. On a typical design, routing delay is comparable to or larger than LUT delay, which is why a design that is “only 30 % full” can still fail timing when the logic is spread across the die. The chosen state of every mux, every LUT table and every flip-flop option is written to configuration memory at power-up. Most devices hold that memory in SRAM, which is why they need an external flash or a host to load them. Some Lattice, Microchip and Gowin parts use flash or antifuse configuration and come up without a loader.

Hard blocks: block RAM, DSP and clocking

Block RAM (BRAM) is a column of true dual-port memories, typically 18 Kb or 36 Kb each on AMD parts and 20 Kb (M20K) on Altera. DSP slices contain a multiplier (27 by 18 bits on AMD UltraScale, variable precision on Altera) with a pre-adder and an accumulator, pipelined to run at the fabric’s top clock. Clock management tiles (MMCM and PLL on AMD, IOPLL and fPLL on Altera) synthesise clocks and remove skew, and a tree of global and regional buffers distributes them. The I/O ring adds programmable standards, delay lines, serialisers and, on larger parts, gigabit transceivers. The ratio of these blocks to plain logic is the real difference between device families, and it is the ratio your application cares about.

Newer tile types

Larger devices add coarser structures. AMD Versal places an array of vector processors (AI Engines) and a network on chip beside the fabric. Altera Agilex has hardened memory controllers and a hyper-registered routing fabric. Achronix has machine-learning processors and a network on chip in Speedster7t. Lattice and Efinix instead keep tiles small and spend area on low power. Which of these is “better” depends entirely on the workload.

Where to start

The beginner track builds this picture one lesson at a time:

Intermediate lessons on routing, clocking and hard-block inference are coming.

Tools and vendors

Vendor Logic cell Block RAM DSP Tool Hub
AMD 6-input LUT, CLB slices 18/36 Kb BRAM, UltraRAM DSP48E2, DSP58 Vivado /vendors/amd/
Altera 8-input ALM M20K Variable-precision DSP Quartus Prime /vendors/altera/
Microchip 4-input LUT (PolarFire) LSRAM 20 Kb, uSRAM Math block 18x18 Libero SoC /vendors/microchip/
Lattice 4-input LUT EBR 9/18 Kb sysDSP Radiant, Diamond /vendors/lattice/
Efinix 4-input LUT (XLR) 5/10 Kb 18x19 multiplier Efinity /vendors/efinix/
Gowin 4-input LUT BSRAM 18 Kb 18x18 multiplier Gowin EDA /vendors/gowin/

Block sizes above are the common cases at the time of writing. Check the specific family datasheet before counting resources.

Common mistakes

  • Comparing vendors by “logic cells” or “logic elements” without converting to equivalent LUT4 or LUT6 counts.
  • Writing a memory that does not match the block RAM template, so it is built from thousands of flip-flops instead.
  • Assuming an unused resource is free. An idle block RAM still consumes static power and occupies a column that may block placement.
  • Driving a clock from logic (a gated or divided clock) instead of using the clock manager and clock enables.
  • Reading only the headline frequency. The fabric’s maximum clock rarely survives a real design with real routing.
  • Ignoring the configuration path until board bring-up, then discovering the flash footprint or boot mode pins were wrong.

Going deeper