Altera announces Agilex 2X, with Agilex 27 first and silicon not due until 2027
Altera's Innovators Day launch covers four families, a third-generation HyperFlex fabric and the QuartusIQ assistant in Quartus Prime 26.3. Engineering samples of Agilex 27 are expected in the second half of 2027.
Altera used its Innovators Day event on 28 October 2026 to announce Agilex 2X, a portfolio of FPGAs and SoC FPGAs split into four families. Agilex 27 is the high-performance tier for terabit networking, 6G and beamforming. Agilex 25 is the mid-range family aimed at video and low-latency sensors. Agilex 23 adds embedded compute and functional safety for robotics and industrial control. Agilex 22 is the high-I/O-density family for bridging, motor control and board management.
Only Agilex 27 has been detailed so far. CNX Software’s summary of the product tables lists 14 devices, from 866k to 17.6 million logic elements, with optional dual Cortex-A720 and dual Cortex-A520 cores at up to 2.3 GHz. Hard blocks include up to ten ports of 800GbE or four of 1.6TbE, PCIe 6.0 and 7.0 controllers, transceivers at up to 256 Gbps, and DDR5, LPDDR5X and LPDDR6 memory controllers. A new on-chip network, HyperFlow, carries traffic between interfaces, memory and the fabric without consuming soft logic. Altera claims 1.8 times the performance per watt of Agilex 7, according to the company’s own comparison.
The software side is QuartusIQ, an AI assistant built into Quartus Prime Pro 26.3 that also exposes a Model Context Protocol connector for external editors. Altera says it speeds design creation by up to 10 times, based on internal benchmarks. Quartus Prime support for Agilex 27 reaches early-access customers in mid-November 2026. Engineering samples are expected in the second half of 2027, and pricing has not been announced.
Why it matters
This is a roadmap announcement, not a part you can order. The silicon is at least nine months away, and the families most readers would use, Agilex 23 and 22, have no published tables yet. The interesting architectural change is HyperFlow: a hardened data network, similar in spirit to the NoC in AMD Versal, that takes bulk data movement out of the LUT fabric. Whether it is as flexible as soft interconnect is the question to ask when early-access documentation appears. Treat the 1.8x and 10x figures as vendor claims until independent measurements exist.