Learn FPGA design, in order
Four tracks, each lesson building on the last. Every lesson states its objectives, shows a diagram, gives HDL that actually compiles, and ends with an exercise.
From “what is an FPGA?” to your first synthesised design on a real board.
What is an FPGA?
A field-programmable gate array is a chip whose logic you wire up yourself. This lesson explains what that means, how it differs from a microcontroller, an ASIC and a GPU, and where FPGAs earn their keep
How an FPGA is programmed
The path from a hardware description to a configured chip, step by step, with the tool names you will meet at AMD, Altera, Lattice and in the open-source flow
Combinational logic and look-up tables
Boolean functions, truth tables and how a look-up table turns any of them into a small memory, plus carry chains and multiplexers, with a combinational block in Verilog and VHDL
Registers, clocks and the idea of state
Flip-flops, clock edges, setup and hold explained intuitively, the synchronous design rules that keep a design predictable, and a register with synchronous reset and enable in Verilog and VHDL
Your first HDL module
The anatomy of a Verilog module and a VHDL entity, ports, wires, regs and signals, continuous and clocked assignment, and a complete blinking-LED counter in both languages explained line by line
Simulation and testbenches
Why you simulate before you synthesise, how a Verilog or VHDL testbench drives a design, and how to read the waveform it produces.
Finite state machines
Moore and Mealy machines, how to encode states, the two-process and one-process coding styles, and the bugs that catch out every beginner's first FSM.
Counters, timers and debouncing
Clock enables instead of divided clocks, a millisecond tick generator, a button debouncer with edge detection, and a multiplexed seven-segment display, all with a testbench.
Memories, block RAM and FIFOs
Distributed versus block RAM, how to write RAMs and ROMs so synthesis infers the right primitive, read-before-write against write-first, and a synchronous FIFO with full and empty flags.
From RTL to board: the full flow
Constraints files for AMD, Altera, Lattice and Gowin, pin assignment and I/O standards, what the timing report tells you, and a worked blinky on the Basys 3 and the Tang Nano 9K.
Timing, constraints, clock domains, verification and bus interfaces.
Lessons for this track are being written. The beginner track is the place to start.
SoC FPGAs, high-speed I/O, DSP pipelines and hardware acceleration.
Lessons for this track are being written. The beginner track is the place to start.
Architecture research, CAD algorithms, security and the open-source frontier.
Lessons for this track are being written. The beginner track is the place to start.