<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"><channel><title>FPGA Guide — news</title><description>Daily FPGA news briefs in plain English, with sources.</description><link>https://www.fpgaguide.com/</link><language>en-gb</language><item><title>AMD announces Versal TR devices with a protection die bonded over the silicon backside</title><link>https://www.fpgaguide.com/news/2026-11-12-amd-versal-tr-tamper-resistant/</link><guid isPermaLink="true">https://www.fpgaguide.com/news/2026-11-12-amd-versal-tr-tamper-resistant/</guid><description>Three tamper-resistant Versal AI Edge Gen 2 parts add a sensor die covering the chip backside, post-quantum signature acceleration and new glitch detectors. Samples are due in the second half of 2027.</description><pubDate>Thu, 12 Nov 2026 00:00:00 GMT</pubDate><category>hardware-security</category><category>soc-fpgas</category><category>amd</category></item><item><title>Yosys 0.71 reimplements strings and lifts the multiplier size limit in the MCM pass</title><link>https://www.fpgaguide.com/news/2026-11-12-yosys-0-71-released/</link><guid isPermaLink="true">https://www.fpgaguide.com/news/2026-11-12-yosys-0-71-released/</guid><description>The November release of the open-source synthesis tool changes its internal string storage, which may break plugins, adds a shuffle pass and FPGA target options, and fixes out-of-memory crashes on large case statements.</description><pubDate>Thu, 12 Nov 2026 00:00:00 GMT</pubDate><category>open-source-toolchains</category><category>hdl-languages</category><category>opensource</category></item><item><title>Lattice and NXP pair Nexus FPGAs with the i.MX 95 over PCIe for industrial edge designs</title><link>https://www.fpgaguide.com/news/2026-11-10-lattice-nxp-pcie-companion/</link><guid isPermaLink="true">https://www.fpgaguide.com/news/2026-11-10-lattice-nxp-pcie-companion/</guid><description>The Lattice NXP PCIe Companion solution puts a Certus-NX or CertusPro-NX beside NXP&apos;s i.MX 95 applications processor for deterministic I/O, interface bridging and hardware-rooted security.</description><pubDate>Tue, 10 Nov 2026 00:00:00 GMT</pubDate><category>soc-fpgas</category><category>hardware-security</category><category>high-speed-io</category><category>lattice</category></item><item><title>QuickLogic lands 16 nm automotive eFPGA win as revenue rises 153 per cent</title><link>https://www.fpgaguide.com/news/2026-11-10-quicklogic-q3-2026-efpga-win/</link><guid isPermaLink="true">https://www.fpgaguide.com/news/2026-11-10-quicklogic-q3-2026-efpga-win/</guid><description>Third-quarter revenue of 5.1 million US dollars, a narrower loss and a six-figure eFPGA Hard IP licence for an automotive and industrial SoC aimed at battery management and motor control.</description><pubDate>Tue, 10 Nov 2026 00:00:00 GMT</pubDate><category>efpga-and-adaptive-asics</category><category>careers-and-industry</category><category>quicklogic</category></item><item><title>AT&amp;T UNIX PC recreated in FPGA logic for the MiSTer platform</title><link>https://www.fpgaguide.com/news/2026-11-08-unix-pc-mister-core/</link><guid isPermaLink="true">https://www.fpgaguide.com/news/2026-11-08-unix-pc-mister-core/</guid><description>Hrvoje Cavrak&apos;s core reproduces the 1985 workstation&apos;s 68010, MMU, disk controllers, video and even its modem on a DE10-Nano, with parts of the code written with help from LLM tools.</description><pubDate>Sun, 08 Nov 2026 00:00:00 GMT</pubDate><category>boards-and-kits</category><category>hdl-languages</category><category>altera</category><category>opensource</category></item><item><title>Lattice reports record quarter as FPGA revenue climbs about 90 per cent</title><link>https://www.fpgaguide.com/news/2026-11-02-lattice-q3-2026-results/</link><guid isPermaLink="true">https://www.fpgaguide.com/news/2026-11-02-lattice-q3-2026-results/</guid><description>Third-quarter revenue reached 291.0 million US dollars, up 118 per cent year on year, with data centre AI demand driving the Compute and Communications segment. The total includes two months of the AMI acquisition.</description><pubDate>Mon, 02 Nov 2026 00:00:00 GMT</pubDate><category>careers-and-industry</category><category>data-centre-and-acceleration</category><category>lattice</category></item><item><title>Microchip adds EtherCAT and TSN IP to its PolarFire FPGA and SoC platform</title><link>https://www.fpgaguide.com/news/2026-10-29-microchip-polarfire-ethercat-tsn/</link><guid isPermaLink="true">https://www.fpgaguide.com/news/2026-10-29-microchip-polarfire-ethercat-tsn/</guid><description>Beckhoff&apos;s EtherCAT IP and Microchip&apos;s own TSN IP join the PolarFire industrial networking stack, with a dual gigabit Ethernet FMC card and the PolarFire SoC Video Kit offered for prototyping.</description><pubDate>Thu, 29 Oct 2026 00:00:00 GMT</pubDate><category>soc-fpgas</category><category>high-speed-io</category><category>microchip</category></item><item><title>Altera announces Agilex 2X, with Agilex 27 first and silicon not due until 2027</title><link>https://www.fpgaguide.com/news/2026-10-28-altera-agilex-2x-portfolio/</link><guid isPermaLink="true">https://www.fpgaguide.com/news/2026-10-28-altera-agilex-2x-portfolio/</guid><description>Altera&apos;s Innovators Day launch covers four families, a third-generation HyperFlex fabric and the QuartusIQ assistant in Quartus Prime 26.3. Engineering samples of Agilex 27 are expected in the second half of 2027.</description><pubDate>Wed, 28 Oct 2026 00:00:00 GMT</pubDate><category>fpga-architecture</category><category>high-speed-io</category><category>ai-ml</category><category>altera</category></item></channel></rss>