Structured lessons, deep-dive topic hubs, vendor and board references, and daily FPGA news written in plain English. From first LUT to research frontier.https://www.fpgaguide.com/en-gbhttps://www.fpgaguide.com/learn/beginner/01-what-is-an-fpga/https://www.fpgaguide.com/learn/beginner/01-what-is-an-fpga/A field-programmable gate array is a chip whose logic you wire up yourself. This lesson explains what that means, how it differs from a microcontroller, an ASIC and a GPU, and where FPGAs earn their keepFri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/learn/beginner/02-how-an-fpga-is-programmed/https://www.fpgaguide.com/learn/beginner/02-how-an-fpga-is-programmed/The path from a hardware description to a configured chip, step by step, with the tool names you will meet at AMD, Altera, Lattice and in the open-source flowFri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/learn/beginner/03-combinational-logic-and-luts/https://www.fpgaguide.com/learn/beginner/03-combinational-logic-and-luts/Boolean functions, truth tables and how a look-up table turns any of them into a small memory, plus carry chains and multiplexers, with a combinational block in Verilog and VHDLFri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/learn/beginner/04-registers-clocks-and-state/https://www.fpgaguide.com/learn/beginner/04-registers-clocks-and-state/Flip-flops, clock edges, setup and hold explained intuitively, the synchronous design rules that keep a design predictable, and a register with synchronous reset and enable in Verilog and VHDLFri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/learn/beginner/05-your-first-hdl-module/https://www.fpgaguide.com/learn/beginner/05-your-first-hdl-module/The anatomy of a Verilog module and a VHDL entity, ports, wires, regs and signals, continuous and clocked assignment, and a complete blinking-LED counter in both languages explained line by lineFri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/learn/beginner/06-simulation-and-testbenches/https://www.fpgaguide.com/learn/beginner/06-simulation-and-testbenches/Why you simulate before you synthesise, how a Verilog or VHDL testbench drives a design, and how to read the waveform it produces.Fri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/learn/beginner/07-finite-state-machines/https://www.fpgaguide.com/learn/beginner/07-finite-state-machines/Moore and Mealy machines, how to encode states, the two-process and one-process coding styles, and the bugs that catch out every beginner's first FSM.Fri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/learn/beginner/08-counters-timers-and-debouncing/https://www.fpgaguide.com/learn/beginner/08-counters-timers-and-debouncing/Clock enables instead of divided clocks, a millisecond tick generator, a button debouncer with edge detection, and a multiplexed seven-segment display, all with a testbench.Fri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/learn/beginner/09-memories-block-ram-and-fifos/https://www.fpgaguide.com/learn/beginner/09-memories-block-ram-and-fifos/Distributed versus block RAM, how to write RAMs and ROMs so synthesis infers the right primitive, read-before-write against write-first, and a synchronous FIFO with full and empty flags.Fri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/learn/beginner/10-from-rtl-to-board/https://www.fpgaguide.com/learn/beginner/10-from-rtl-to-board/Constraints files for AMD, Altera, Lattice and Gowin, pin assignment and I/O standards, what the timing report tells you, and a worked blinky on the Basys 3 and the Tang Nano 9K.Fri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/projects/blinky-to-pwm-tang-nano-9k/https://www.fpgaguide.com/projects/blinky-to-pwm-tang-nano-9k/Install Yosys, nextpnr-himbaechel and openFPGALoader, then make the six LEDs on the Tang Nano 9K breathe with a triangle wave, a gamma lookup and a PWM module you write yourself.Fri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/projects/uart-loopback-basys3/https://www.fpgaguide.com/projects/uart-loopback-basys3/Build a 115200-baud UART receiver and transmitter in Verilog, echo typed characters back with their case toggled, simulate it, then test it from a serial terminal.Fri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/projects/vga-pattern-icebreaker/https://www.fpgaguide.com/projects/vga-pattern-icebreaker/Generate 640x480 at 60 Hz from an iCE40 UP5K with the open-source flow, with a PLL-derived pixel clock, a sync generator, colour bars, a chequerboard and a bouncing block on a 12-bit VGA Pmod.Fri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/projects/axi-gpio-pynq-z2/https://www.fpgaguide.com/projects/axi-gpio-pynq-z2/Write an AXI4-Lite slave with four registers by hand, drop it into a Zynq block design, export the hardware, and drive it from Python on PYNQ or from bare-metal C in Vitis.Fri, 13 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/news/2026-11-12-amd-versal-tr-tamper-resistant/https://www.fpgaguide.com/news/2026-11-12-amd-versal-tr-tamper-resistant/Three tamper-resistant Versal AI Edge Gen 2 parts add a sensor die covering the chip backside, post-quantum signature acceleration and new glitch detectors. Samples are due in the second half of 2027.Thu, 12 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/news/2026-11-12-yosys-0-71-released/https://www.fpgaguide.com/news/2026-11-12-yosys-0-71-released/The November release of the open-source synthesis tool changes its internal string storage, which may break plugins, adds a shuffle pass and FPGA target options, and fixes out-of-memory crashes on large case statements.Thu, 12 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/news/2026-11-10-lattice-nxp-pcie-companion/https://www.fpgaguide.com/news/2026-11-10-lattice-nxp-pcie-companion/The Lattice NXP PCIe Companion solution puts a Certus-NX or CertusPro-NX beside NXP's i.MX 95 applications processor for deterministic I/O, interface bridging and hardware-rooted security.Tue, 10 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/news/2026-11-10-quicklogic-q3-2026-efpga-win/https://www.fpgaguide.com/news/2026-11-10-quicklogic-q3-2026-efpga-win/Third-quarter revenue of 5.1 million US dollars, a narrower loss and a six-figure eFPGA Hard IP licence for an automotive and industrial SoC aimed at battery management and motor control.Tue, 10 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/research/2026-11-10/https://www.fpgaguide.com/research/2026-11-10/Eight recent arXiv papers on LUT-based and ternary inference, zero-skipping CNN engines, anti-tamper sensor weaknesses, homomorphic encryption, an open Spartan-6 flow, SoC simulation and HLS modelling.Tue, 10 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/news/2026-11-08-unix-pc-mister-core/https://www.fpgaguide.com/news/2026-11-08-unix-pc-mister-core/Hrvoje Cavrak's core reproduces the 1985 workstation's 68010, MMU, disk controllers, video and even its modem on a DE10-Nano, with parts of the code written with help from LLM tools.Sun, 08 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/news/2026-11-02-lattice-q3-2026-results/https://www.fpgaguide.com/news/2026-11-02-lattice-q3-2026-results/Third-quarter revenue reached 291.0 million US dollars, up 118 per cent year on year, with data centre AI demand driving the Compute and Communications segment. The total includes two months of the AMI acquisition.Mon, 02 Nov 2026 00:00:00 GMThttps://www.fpgaguide.com/news/2026-10-29-microchip-polarfire-ethercat-tsn/https://www.fpgaguide.com/news/2026-10-29-microchip-polarfire-ethercat-tsn/Beckhoff's EtherCAT IP and Microchip's own TSN IP join the PolarFire industrial networking stack, with a dual gigabit Ethernet FMC card and the PolarFire SoC Video Kit offered for prototyping.Thu, 29 Oct 2026 00:00:00 GMThttps://www.fpgaguide.com/news/2026-10-28-altera-agilex-2x-portfolio/https://www.fpgaguide.com/news/2026-10-28-altera-agilex-2x-portfolio/Altera's Innovators Day launch covers four families, a third-generation HyperFlex fabric and the QuartusIQ assistant in Quartus Prime 26.3. Engineering samples of Agilex 27 are expected in the second half of 2027.Wed, 28 Oct 2026 00:00:00 GMT