Toolchain matrix

This page is for anyone choosing or installing an FPGA toolchain. It lists the vendor suites and the open-source flow side by side: what runs on your machine, what the free tier covers and roughly how long a build takes. Versions were checked on 13 November 2026 and move quickly.

How to read the classes

Class	Download size	Typical compile time (small design, under 10k LUTs)
S	under 1 GB	seconds to a minute
M	1 to 10 GB	one to five minutes
L	10 to 50 GB	five to twenty minutes
XL	over 50 GB with all device families (selective install reduces it)	tens of minutes, hours for large SoC or Versal designs

Compile time depends on the device, the design and your CPU more than on the tool, so the class is a first guess.

AMD

Tool	Version at time of writing	OS	Licence tiers and free coverage	Size	Compile	Notes
Vivado	2026.1 (2026.1.1 patch)	Windows 10/11, RHEL and Ubuntu LTS	New tiered model from 2026.1: Basic (free, annual renewal, all 7 series and lower-end UltraScale and UltraScale+), Core and Pro (annual, paid), Enterprise and Gold (perpetual, paid). Third-party reports in 2026 said Basic was Windows-only, so check the AMD licensing page before planning on free Linux use.	XL	L to XL	Selective device install since 2025.1. Basic does not get minor (x.y.1) releases.
Vitis	2026.1	Same as Vivado	Follows the Vivado tier	XL	n/a	Needed for HLS and Versal AI Engine work.
ISE	14.7 (frozen)	Windows 7 era, or a Linux virtual machine image	Free WebPACK	L	M	Spartan-6 and older only. Do not start new work on it.

Altera

Tool	Version	OS	Licence tiers and free coverage	Size	Compile	Notes
Quartus Prime Pro	26.3	Windows 10/11, RHEL and Ubuntu LTS	Paid subscription. A one-year no-cost licence is offered for Agilex 5 E-Series devices, renewable from inside the tool. 90-day evaluation on request.	L	L to XL	Agilex, Stratix 10, Arria 10, Cyclone 10 GX. Different project format from Standard.
Quartus Prime Standard	25.1std	Same	Paid annual subscription	L	L	Older families (Arria V, Cyclone V, Stratix V) not in Pro. Shares a release stream with Lite.
Quartus Prime Lite	25.1std	Same	Free, no licence file	M	M	Cyclone IV, Cyclone V, Cyclone 10 LP, MAX II, MAX V, MAX 10, one Arria II part. Covers most hobby and teaching boards.

Microchip

Tool	Version	OS	Licence tiers and free coverage	Size	Compile	Notes
Libero SoC	2026.1	Windows 11, RHEL 9, AlmaLinux 9, Ubuntu 24.04 (Windows 10 dropped in 2025.1)	Silver (free, most small and mid devices, with the MPF300TS and MPFS250TC added in 2026.1), Gold and Platinum (paid, large devices and extra tools)	L	M to L	Bundles Synplify Pro ME. 2026.1 is the last release with ModelSim ME Pro.

Lattice

Tool	Version	OS	Licence tiers and free coverage	Size	Compile	Notes
Radiant	2026.1 (2026.1.1 patch)	Windows 10/11, Linux (RHEL and Ubuntu)	Free licence (node-locked or floating) for iCE40 UltraPlus, CrossLink-NX, Certus-NX, MachXO3D/MachXO5 and others. Subscription needed for Avant and for some larger Nexus parts, and for bundled IP such as PCIe and DDR4 since 2025.2.	M	S to M	Propel adds the RISC-V SoC builder.
Diamond	3.14	Windows 10/11, Linux	Free licence for most devices	M	S to M	ECP5, MachXO2, MachXO3. Simulation moved to a QuestaSim OEM edition in 3.14, which needs a regenerated licence.

Efinix and Gowin

Tool	Version	OS	Licence tiers and free coverage	Size	Compile	Notes
Efinity	2026.1	Windows 10/11, Ubuntu LTS	Free after account registration. One licence covers all Trion and Titanium devices, with free maintenance renewals.	M	S to M	2026.1 added a partition planner and faster place and route.
Gowin EDA	1.9.12 (service packs through 2026)	Windows, Linux, macOS (Education edition)	Education edition needs no licence file but supports fewer devices and IP. Standard edition needs a free licence requested from Gowin and covers all devices.	M	S to M	Tang Nano boards with the CH552 USB bridge need the Standard edition.

Open source

Tool	Version	OS	Licence	Size	Compile	Notes
Yosys	0.71 (November 2026)	Linux, macOS, Windows	ISC, free	S	S	Synthesis, monthly releases. Reads Verilog 2005 and a SystemVerilog subset, VHDL via the GHDL plugin.
nextpnr	0.11.1	Linux, macOS, Windows	ISC, free	S	S	Place and route. One binary per architecture family, plus the himbaechel generic backend used for Gowin and GateMate.
Verilator	5.054 (November 2026)	Linux, macOS, Windows via WSL or MSYS2	LGPL-3 or Artistic, free	S	S (compiles to C++, so first build takes longer)	Fastest open simulator. Two-state, with timing support since version 5.
Icarus Verilog	13.0	Linux, macOS, Windows	GPL-2, free	S	S	Event-driven Verilog and a SystemVerilog subset. Slow for large designs, easy to install.
GHDL	6.0.0 (March 2026)	Linux, macOS, Windows	GPL-2, free	S	S	VHDL-2008 simulator with three back ends (mcode, LLVM, GCC). The yosys plugin adds VHDL synthesis.
cocotb	2.1.0	Any with Python 3.9 or newer	BSD-3, free	S	n/a	Python testbenches driving Icarus, Verilator, GHDL, Questa and others. The 2.0 API broke 1.x testbenches.
OSS CAD Suite	nightly	Linux, macOS, Windows	Mixed, free	M	n/a	YosysHQ’s one-archive bundle of all the above. The easiest install.

Which devices do open-source tools support?

Support means Yosys plus nextpnr (or an equivalent open flow) can take Verilog to a bitstream without the vendor tool.

Vendor and family	Project	Status at time of writing	Notes
Lattice iCE40 (all)	IceStorm	Mature	The reference flow, used in production.
Lattice ECP5	Project Trellis	Mature	SERDES and DDR primitives covered. Most capable open target.
Lattice Nexus (CrossLink-NX, Certus-NX, CertusPro-NX)	prjoxide	Usable	Less field testing than ECP5. Some hard blocks not yet covered.
Gowin GW1N, GW1NR, GW2A, GW5A	Apicula (nextpnr-himbaechel)	Usable for GW1N and GW2A, improving for GW5A	Tang Nano and Tang Primer boards are the common targets.
AMD 7 series (Artix, Kintex, Zynq-7000)	Project X-Ray via openXC7	Experimental to usable	Fabric and block RAM work, DSP and transceivers limited. No UltraScale.
AMD Spartan-6 and older	none	Not supported
Altera Cyclone V	Mistral	Experimental	Fabric documented; place and route still immature.
Altera Agilex, Stratix, Arria	none	Not supported
Microchip PolarFire, SmartFusion2	none	Not supported	Microchip’s own flow only.
Efinix Trion, Titanium	none	Not supported	Efinity is free, so the pressure is low.
QuickLogic EOS S3, PolarPro 3	QuickLogic open flow (Yosys plus VPR)	Usable	The one vendor that ships an open flow as its primary tool.
Cologne Chip GateMate	Yosys plus nextpnr-himbaechel, or the vendor’s P&R	Usable, vendor supported

Simulation and synthesis to a netlist work for any vendor. The table is only about producing a bitstream.