AMD (Xilinx)
The largest FPGA vendor by revenue, with the widest range from 28 nm Spartan parts to 6 nm Versal adaptive SoCs, and the Vivado and Vitis tools most engineers meet first.
| Headquarters | Santa Clara, California, USA |
|---|---|
| Website | www.amd.com/en/products/adaptive-socs-and-fpgas.html |
| Toolchain | Vivado (RTL to bitstream), Vitis and Vitis HLS (software and C++ synthesis), PetaLinux (embedded Linux) |
| Licensing | Free Vivado Standard edition covers 7 series, Zynq 7000 and smaller UltraScale+ and Versal parts; larger devices need a paid Enterprise licence |
| Updated | 13 Nov 2026 |
Device families #
| Family | Process | Logic | Positioning |
|---|---|---|---|
| Spartan 7 | 28 nm | 6k-102k logic cells | Lowest-cost 7 series, no transceivers |
| Spartan UltraScale+ | 16 nm | about 11k-218k logic cells | Cost-optimised successor with more I/O per logic cell |
| Artix 7 | 28 nm | 12.8k-215k logic cells | Low-cost with 6.6 Gb/s transceivers |
| Artix UltraScale+ | 16 nm | about 81k-308k logic cells | Low-cost with 16 Gb/s transceivers and PCIe Gen4 |
| Kintex 7 | 28 nm | 65k-477k logic cells | Mid-range price and performance |
| Kintex UltraScale / UltraScale+ | 20 nm / 16 nm | 318k-1,451k (US) and 356k-1,143k (US+) system logic cells | Mid-range with 16 Gb/s and 32 Gb/s transceivers |
| Virtex 7 | 28 nm | 326k-1,955k logic cells | Highest capacity 7 series |
| Virtex UltraScale / UltraScale+ | 20 nm / 16 nm | up to about 8.9M system logic cells (VU19P) | Largest capacity, 58 Gb/s transceivers, HBM variants |
| Zynq 7000 | 28 nm | 23k-444k logic cells | Dual Cortex-A9 plus 7 series fabric |
| Zynq UltraScale+ MPSoC and RFSoC | 16 nm | 103k-1,143k system logic cells | Quad Cortex-A53, dual Cortex-R5, GPU, optional RF data converters |
| Versal (AI Core, AI Edge, Prime, Premium, HBM) | 7 nm | see datasheet, varies widely by series | Adaptive SoC with network on chip, Cortex-A72, optional AI Engines |
| Versal Gen 2 | 6 nm | see datasheet | Second generation with Cortex-A78AE and Cortex-R52, newer AI Engines |
Who they are
This page is for anyone choosing or learning an AMD device, and for engineers coming from another vendor who need to know what is different. AMD acquired Xilinx in February 2022, and the Xilinx name survives in part numbers (XC7A100T), file formats and older documentation. Xilinx invented the commercial FPGA in 1985 and held the largest market share for most of the decades since. The product line today spans the 28 nm 7 series, which is still shipping in volume, through UltraScale and UltraScale+, to Versal adaptive SoCs on 7 nm and 6 nm. If a university course or a hobby tutorial names a specific chip, it is more often than not an Artix 7 or a Zynq 7000.
Toolchain
You install Vivado. The ML edition unified installer is a web download of a few gigabytes that then fetches what you select. A full install with Vitis takes well over 100 GB of disk, so choose devices carefully in the installer. Supported hosts are 64-bit Windows and a short list of Linux distributions (Ubuntu LTS, RHEL and compatible rebuilds). macOS is not supported, though Vivado runs acceptably in a Linux virtual machine or on an x86 cloud instance.
At the time of writing the Standard edition is free after registration and covers Spartan 7, Artix 7, Zynq 7000, most Kintex 7 parts, Artix UltraScale+, a few Kintex and Zynq UltraScale+ devices, and the smaller Versal AI Edge and Prime parts. Larger devices need an Enterprise licence, which is typically node-locked or floating and priced per seat. Vitis, Vitis HLS and PetaLinux are free. Check the current device table before buying a board, because the free device list has grown over time.
Pain points are well known. Run times are long compared to smaller vendors’ tools, the GUI is heavy, and projects do not version well unless you drive the tool from Tcl scripts and keep the generated project directory out of source control. The IP Integrator block design is powerful but produces a lot of generated code that is awkward to review. Vitis has been through several reorganisations and tutorials written for one year’s release often fail on the next.
Boards to start with
- The Basys 3 (Artix 7 35T) has switches, LEDs, seven-segment displays and a VGA port, which makes it ideal for first lessons.
- The Arty A7-100T gives you DDR3, Ethernet and Pmod headers at a modest price, and the 100T part is large enough for a MicroBlaze or a VexRiscv system.
- The Cmod A7-35T is a breadboard-friendly module when you want to wire the FPGA to real hardware.
- The Zybo Z7-20 or the PYNQ-Z2 are the usual entry points to Zynq 7000, with Linux running on the Cortex-A9 cores.
- The Kria KV260 puts a Zynq UltraScale+ MPSoC on a vision-oriented carrier for a price close to a hobby board.
Migration notes
If you are coming from Altera, the first change is constraints. Vivado uses XDC, which is SDC with Tcl extensions, and you write pin locations, I/O standards and timing in the same file. Period constraints go on the input port or clock pin, not on an internal net, and get_clocks returns generated clocks from MMCM and PLL primitives automatically once the input clock is constrained.
Primitive names differ. Altera’s ALM becomes AMD’s CLB slice with 6-input LUTs. The clocking primitives are MMCM and PLL, usually instantiated through the Clocking Wizard. Block RAM is 36 kb (RAMB36E1 on 7 series, RAMB36E2 on UltraScale). Global clock buffers are BUFG, with regional BUFR and BUFH variants that catch people out. Infer memory and DSP from RTL where you can, because inference is portable and the templates in the synthesis guide are reliable.
Platform Designer becomes IP Integrator. AXI is the interconnect standard throughout, which is a help if you know it and a learning curve if you do not. Signal Tap becomes the Integrated Logic Analyser (ILA), inserted either as an IP block or with a MARK_DEBUG attribute.
Watch for
The free Standard edition excludes some mid-range parts that appear on affordable boards, so check the licence list before buying. Vivado versions are released roughly twice a year and board files, IP versions and Vitis platforms move with them, so pin your project to one release. Versal is not a drop-in successor to UltraScale+: the network on chip, the platform management controller and the AI Engine flow change how you build and boot a design. Zynq boot and PetaLinux configuration are a frequent source of lost days, so start from the vendor’s board support package and change one thing at a time. Finally, old Xilinx documentation URLs have moved to the AMD domain, and many forum answers point at pages that no longer exist.