The timing and pin constraints you write every week in Vivado XDC and Quartus SDC, with Lattice equivalents, worked patterns and a table of common mistakes. · verified 13 Nov 2026
Channels, the handshake rule, signal tables, burst types, response codes and the bugs that show up in every first AXI design, on one page. · verified 13 Nov 2026
Setup and hold inequalities, fmax from slack, synchroniser MTBF, I/O timing budgets, DDR window arithmetic, pipelining gain and fixed-point bit growth, all in plain text. · verified 13 Nov 2026
A Rosetta table of the constructs you write every day in VHDL-2008, Verilog-2001 and SystemVerilog, with compiled snippets for the ones a table cannot hold. · verified 13 Nov 2026
Every mainstream FPGA toolchain and the open-source flow on one page, with versions, OS support, licence tiers, download and compile-time classes. · verified 13 Nov 2026
The reset synchroniser, two-flop synchroniser, pulse and handshake synchronisers, Gray-pointer FIFO and the constraints that make them safe, with compiled Verilog. · verified 13 Nov 2026