AXI4, AXI4-Lite and AXI4-Stream cheat sheet

This page is for engineers writing or debugging an AXI interface by hand. It covers the three variants you meet on FPGAs: full AXI4 for memory-mapped bursts, AXI4-Lite for registers, and AXI4-Stream for data without addresses. Arm’s AMBA specification is the authority. The versions below are what vendor IP and SoC fabrics on AMD, Altera and Microchip devices expect at the time of writing.

The one rule

Every channel is a VALID/READY pair. A transfer happens on the clock edge where both are high.

Rule	Consequence
The source asserts VALID when it has data and must keep VALID high, with the payload unchanged, until READY is seen high	You cannot pull VALID back because the sink is slow
VALID must not depend on READY	A source that waits for READY before raising VALID can deadlock against a sink that waits for VALID before raising READY
READY may depend on VALID	A sink is allowed to wait for VALID before asserting READY, although it costs a cycle
READY may be asserted before VALID and may be dropped before VALID arrives	A high READY with VALID low is not a transfer
Reset: VALID must be low during and for the first cycle after reset	Drive it from a reset flop, never from combinational logic that could glitch

Channels

Variant	Channels	Purpose
AXI4	AW, W, B, AR, R	Write address, write data, write response, read address, read data. Reads and writes are independent and can be outstanding at once.
AXI4-Lite	same five	One transfer per transaction, no bursts, no IDs, 32-bit or 64-bit data only
AXI4-Stream	T	One channel. No address. Data flows from source (master) to sink (slave).

Channel prefixes appear on every signal (awvalid, wdata, bresp, rlast, tvalid) and vendor IP adds an interface prefix such as s_axi_.

AXI4 signals

Width notes use W for data width in bits and A for address width.

Channel	Signal	Width	Meaning
AW	awaddr	A	Start address of the burst (byte address)
AW	awlen	8	Beats minus one (0 to 255 in AXI4, 0 to 15 in AXI3)
AW	awsize	3	Bytes per beat as log2: 0 = 1 byte, 2 = 4 bytes, 3 = 8 bytes
AW	awburst	2	FIXED, INCR, WRAP (see below)
AW	awid	n	Transaction ID; responses with the same ID return in order
AW	awprot, awcache, awlock, awqos, awregion, awuser	3, 4, 1, 4, 4, n	Attributes. Most FPGA fabrics only honour awprot[1] (secure) and awcache for coherency ports
W	wdata	W	Write data
W	wstrb	W/8	Byte enables, one bit per byte lane
W	wlast	1	High on the final beat of the burst
B	bresp	2	Write response (table below)
B	bid	n	Echo of awid
AR / R	araddr, arlen, arsize, arburst, arid	as AW	Same meanings for reads
R	rdata, rresp, rlast, rid	W, 2, 1, n	Read data and response per beat

AXI4 has no wid. AXI3 had one, and interleaved write data was removed in AXI4.

AXI4-Lite

Signal set	Present	Notes
awaddr, awprot, awvalid, awready	yes	awprot is usually tied to 0
wdata, wstrb, wvalid, wready	yes	wstrb matters for byte writes to registers
bresp, bvalid, bready	yes
araddr, arprot, arvalid, arready	yes
rdata, rresp, rvalid, rready	yes
IDs, len, size, burst, last, lock, cache, qos	no	Every transaction is one beat

A Lite slave may see AW and W in either order. Capture them independently and issue B when both have arrived.

Burst types

awburst or arburst	Name	Address of beat n	Use
0b00	FIXED	same address every beat	FIFO-like peripheral registers
0b01	INCR	start plus n times bytes-per-beat	Normal memory access
0b10	WRAP	increments, wraps at a boundary equal to the burst length in bytes; length must be 2, 4, 8 or 16 beats and the start address must be aligned to the beat size	Cache line fills
0b11	reserved

A burst must not cross a 4 KB address boundary. An INCR burst can be 1 to 256 beats. Narrow transfers (awsize below the bus width) are legal but most FPGA IP prefers full-width beats.

Response codes

bresp or rresp	Name	Meaning
0b00	OKAY	Normal success, or a failed exclusive access
0b01	EXOKAY	Exclusive access succeeded
0b10	SLVERR	Slave reached but returned an error (bad address inside the slave, write to read-only register)
0b11	DECERR	No slave at that address (interconnect decode error)

On a Zynq or Versal processing system a DECERR usually becomes a data abort, so an unmapped address can crash Linux rather than return garbage.

AXI4-Stream

Signal	Width	Required	Meaning
tvalid, tready	1	tvalid yes, tready optional	Handshake. A sink without tready is always ready.
tdata	8n	optional	Payload, an integer number of bytes
tstrb	n	optional	Byte is data (1) or position (0). Rarely used in FPGA IP.
tkeep	n	optional	Byte is valid (1) or null (0). Used for packet tails that do not fill the bus.
tlast	1	optional	Final beat of a packet
tid, tdest	n	optional	Stream identifier and routing target
tuser	n	optional	Sideband bits. Video IP uses it for start-of-frame; Ethernet IP for errors.

AMD IP such as the AXI DMA allows null bytes in tkeep only on the tlast beat, contiguous from lane 0. Sideband meanings are not standardised, so check each core’s product guide.

Common bugs

Bug	What you see	Fix
VALID waits for READY	Deadlock when two such blocks connect, or works only with one vendor’s IP	Assert VALID from state, never from ready
Payload changes while VALID is high and READY low	Corrupt data, protocol checker flags it	Register the payload with the same enable as VALID
wlast missing or on the wrong beat	DMA hangs, interconnect stalls forever	Count beats from awlen plus one
B response before all W beats accepted	Interconnect reorders and data is lost	Issue B only after the beat with wlast
Crossing 4 KB boundary	Works on one slave, fails through an interconnect	Split bursts at 4 KB in the master
Read data returned with the wrong ID order	Reads with the same ID come back out of order	Either use one ID or a reorder buffer
Combinational loop through READY	Timing fails, simulators oscillate	Register READY or cut the loop with a skid buffer
Reset mid-transaction	Slave stuck with outstanding count wrong	Reset both sides together and hold VALID low for a cycle after release
Stream width mismatch	tkeep bits silently dropped by a width converter	Keep tkeep on every stage or none
tready left unconnected on a sink that can stall	Data loss	Connect tready or add a FIFO with back-pressure

Sources

• AMBA AXI Protocol Specification (IHI 0022), Arm Developer
• AMBA AXI-Stream Protocol Specification (IHI 0051), Arm Developer
• UG1037: Vivado Design Suite AXI Reference Guide
• Related on this site: /reference/reset-and-cdc-patterns/ and /topics/soc-fpgas/