Efinix
A younger vendor with the Quantum routing-rich architecture, low-cost Trion devices on 40 nm, 16 nm Titanium parts with hard RISC-V cores, and a free, lightweight Efinity toolchain.
| Headquarters | Santa Clara, California, USA |
|---|---|
| Website | www.efinixinc.com/ |
| Toolchain | Efinity (synthesis, place and route, Interface Designer, debugger), Efinity RISC-V embedded software SDK |
| Licensing | Efinity is free after registration for all devices at the time of writing, node-locked |
| Updated | 13 Nov 2026 |
Device families #
| Family | Process | Logic | Positioning |
|---|---|---|---|
| Trion (T4 to T120) | 40 nm | about 4k-112k logic elements | Low-cost, low-power, small packages |
| Titanium (Ti35 to Ti375) | 16 nm | about 35k-370k logic elements | Higher performance with 16 Gb/s SERDES, hard DDR and hard RISC-V on larger parts |
Who they are
This page is for engineers weighing a lesser-known vendor against the big two, and for anyone curious about an FPGA architecture that is not a copy of the usual LUT-and-routing-switch pattern. Efinix was founded in 2012 in Santa Clara, shipped its first Trion devices in 2018 and followed with the 16 nm Titanium family in 2020. The company’s claim is that its Quantum architecture, in which XLR cells can be used either as logic or as routing, needs less silicon per function than a conventional fabric and so reaches a lower cost and power at a given capacity. It sells mainly into consumer, industrial, medical imaging and edge vision products, and has had a particular following for MIPI camera bridging.
Efinix is small, but it is a serious vendor with multiple generations shipping, which puts it ahead of several better-funded FPGA start-ups that never got that far.
Toolchain
You install Efinity, which runs on 64-bit Windows and Linux (Ubuntu and RHEL-compatible). The install is around 1 GB rather than the tens of gigabytes you may be used to, and compile times for a mid-sized Trion design are minutes rather than tens of minutes. The licence is free at the time of writing, node-locked to a machine identifier and issued through the website for any device including the largest Titanium parts.
The flow has a feature that surprises newcomers. Top-level I/O, PLLs, DDR controllers, MIPI and SERDES are configured in a GUI called the Interface Designer, which generates a periphery template. Your RTL talks to that periphery through plain ports, and you cannot instantiate an I/O buffer or a PLL in RTL. This is tidy once you accept it, but every pin change means a round trip through the GUI or its XML file.
Efinity has no bundled simulator. You use Icarus Verilog, Verilator, ModelSim or Questa with the simulation models Efinix provides. The Efinity Debugger is a logic analyser and virtual I/O tool similar to the ILA. The RISC-V SDK builds software for the Sapphire soft SoC (VexRiscv-based) and for the hard cores on Titanium.
Pain points are a smaller IP catalogue, thinner third-party documentation, no HLS and a community that is small enough that forum questions may go unanswered for a while.
Boards to start with
- The Trion T20 development kit is the vendor’s basic board with enough I/O to learn the Interface Designer flow.
- The Titanium Ti60 development kit adds LPDDR4, MIPI and a camera connector for vision work.
- The Xyloni is a small T8 board at a hobby price, good for a first look without spending much.
Migration notes
Coming from AMD or Altera, the biggest change is the Interface Designer. There are no IBUF, OBUFDS, MMCM or IOPLL primitives to instantiate. Instead you define each pin, PLL and memory interface in the GUI, assign the RTL port names, and let the tool generate the boundary. Clocks come from PLLs defined there, and the output names you choose become the clock ports on your top level.
Timing constraints are an SDC file with the usual create_clock and set_input_delay commands, and the Efinity timing analyser reports in a familiar form. Memory and DSP are inferred from RTL and Efinix publishes coding templates for both. The logic element is a 4-input LUT with a register, so resource counts do not compare one-to-one with 6-input LUT devices: budget roughly 1.5 to 2 Trion LEs per AMD logic cell for the same function.
There is no block design canvas. If you want a SoC, you generate the Sapphire RISC-V SoC with a wizard, and it uses AXI and APB buses that will look familiar.
Watch for
Device availability and lead times have varied, and the larger Titanium parts are newer and less proven in the field than the Trion line. The XLR architecture means routing utilisation can be high on dense designs and timing closure behaves differently from what experience on other fabrics would predict. Interface Designer settings live in an XML file that merges badly in version control. Documentation is adequate but short, and many answers live in the vendor’s support portal rather than public forums. Third-party IP vendors are less likely to have an Efinix port, so budget for writing more yourself.