The open-source ecosystem

Device families #

Who they are

This page treats the open-source toolchain as if it were a vendor, because for many people it is the tool they use. It is for beginners deciding whether to skip the vendor installers, for engineers evaluating the flow for production, and for anyone who wants to know what works and what does not. The ecosystem began in 2013 with Yosys, Claire Wolf’s Verilog synthesis tool, and grew in 2015 with Project IceStorm, which reverse-engineered the iCE40 bitstream and allowed a complete free flow from Verilog to a programmed chip. nextpnr arrived in 2018 as a timing-driven place and route tool with an architecture plug-in model, and projects documenting ECP5, Gowin, Nexus, 7 series and QuickLogic devices followed. YosysHQ, based in Vienna, maintains Yosys, nextpnr and SymbiYosys and sells commercial support and formal verification tools. The rest is maintained by a community of individuals, companies and universities. See also the open-source toolchains topic.

Toolchain

The simplest installation is the OSS CAD Suite, a nightly build from YosysHQ for Linux, macOS and Windows that bundles Yosys, nextpnr for every architecture, openFPGALoader, Icarus Verilog, Verilator, GHDL, SymbiYosys and the solvers it needs. Extract the archive, source the environment script and you are ready. Most Linux distributions also package the tools, though often at older versions. Everything is free and there is no licence file, registration or node locking.

Yosys reads Verilog-2005 and a practical subset of SystemVerilog, with VHDL through the GHDL plugin. nextpnr does placement, routing and timing analysis per architecture. openFPGALoader programs through FTDI, CMSIS-DAP, ST-Link and the Sipeed bridges, covering almost every hobby board. Verilator compiles RTL to C++ for fast simulation, Icarus and GHDL are event-driven simulators for Verilog and VHDL, and cocotb lets you write testbenches in Python against any of them. SymbiYosys drives formal proofs with open SMT solvers. LiteX generates complete SoCs with soft RISC-V cores, DDR controllers and Ethernet, and Amaranth is a Python hardware description language with its own build system.

Pain points: timing analysis in nextpnr handles clock constraints and reports paths but has thinner support for false paths, multi-cycle paths and I/O delays than commercial tools. There is no logic analyser of the ILA kind, though LiteScope fills the gap for LiteX users. Quality of results on large designs is behind the vendor tool, by a margin that varies from small on iCE40 to significant on 7 series.

Boards to start with

• The iCEBreaker was designed for this toolchain and its documentation assumes it.
• The UPduino v3 is the cheapest iCE40 UltraPlus board.
• The ULX3S and the OrangeCrab are the ECP5 boards with full open support and LiteX ports.
• The Tang Nano 9K is the cheapest board of all, supported through Apicula.
• The Fomu fits inside a USB port and runs the full flow, which makes it a good demonstration piece.

Migration notes

Coming from Vivado or Quartus, the first change is that there is no project file. A design is a set of source files, a pin constraint file and a Makefile or a short script: yosys with a synth_ice40 or synth_ecp5 command, then nextpnr-ice40 or nextpnr-ecp5 with the constraints and a target frequency, then a bitstream packer and openFPGALoader. The build is reproducible and fits in version control without effort.

Constraints use the formats of the target: .pcf for iCE40, .lpf for ECP5, .cst for Gowin and .xdc for openXC7. Timing is a --freq argument or clock constraints in the pin file. Primitives are the vendor’s own names (SB_PLL40_CORE, EHXPLLL, rPLL, MMCME2_BASE), and Yosys has simulation models for them. Inference of block RAM, distributed RAM and DSP works, and the templates are the same ones vendor tools accept.

There is no IP catalogue. Soft cores, memory controllers and peripherals come from LiteX, from VexRiscv and NEORV32, or from your own code. Debug is by simulation first, with Verilator fast enough to run software on a simulated SoC.

Watch for

Device coverage is the sharp edge. The flow is complete for iCE40, ECP5 and the small Gowin parts, good for Nexus fabric, and partial for 7 series, where it is usable for learning but not for a design that needs transceivers, PCIe or a hard memory controller. Nothing from Altera, Microchip, Efinix or any UltraScale or Versal device is supported, and bitstream documentation for those does not exist in public. Vendor tools have not stood still either, and the licence terms of AMD and Altera prohibit reverse engineering of their bitstreams, so the 7 series work operates in a grey area that companies may be unwilling to depend on. Finally, nightly builds move fast: pin a release for anything you need to rebuild in a year.