AT&T UNIX PC recreated in FPGA logic for the MiSTer platform
Hrvoje Cavrak's core reproduces the 1985 workstation's 68010, MMU, disk controllers, video and even its modem on a DE10-Nano, with parts of the code written with help from LLM tools.
Hackaday reported on 8 November 2026 on a MiSTer core by Hrvoje Cavrak that recreates the AT&T UNIX PC, a 1985 office workstation built around a 10 MHz Motorola 68010 that ran System V UNIX. The project README describes a mostly cycle-exact 68010 core with the original memory management unit and page map, 512 KB to 4 MB of parity-checked RAM, and the WD1010 hard disk and WD2797 floppy controllers modelled chip by chip, including their DMA path. Disk images live on the SD card.
The periphery is unusually complete. The 720 by 348 monochrome display is drawn as a simulated CRT at 1280 by 720, with phosphor glow and screen curvature. There is a LANCE Ethernet card bridged to the host LAN, a serial console, a virtual line printer and a working telephone interface whose modem tones come out over HDMI audio and whose calls turn into telnet connections. The original boot diagnostics and diagnostic floppy run as well.
The core needs a DE10-Nano with the SDRAM add-on board, because the FPGA’s own memory is under 1 MB and the machine can have 4 MB. The boot ROMs and disk images remain under copyright and are not distributed, so the README points to Bitsavers and other archives instead. Hackaday notes that some of the code was written and validated with LLM coding assistants, a trade-off the author accepted given how hard the real hardware is to obtain. The source mixes SystemVerilog, Verilog and VHDL.
Why it matters
Retro cores are where many engineers learn bus arbitration, DMA and memory management for real, and this one covers all three on a machine with a genuine MMU and swapping. The copyright note deserves attention: the ROM is still owned, so the project ships logic only. The use of LLM assistants for parts of the RTL is a sign of the times. It worked here because the author had the original schematics and a diagnostic suite to validate against, which is the only safe way to use generated HDL.