Vendor hub

Gowin Semiconductor

A Chinese vendor whose LittleBee and Arora devices, sold on cheap Sipeed Tang boards, have become the entry point for many beginners, with Gowin EDA and open-source Apicula support.

Headquarters	Guangzhou, China
Website	www.gowinsemi.com/
Toolchain	Gowin EDA (synthesis, place and route, programmer, analyser), or Yosys and nextpnr-himbaechel through Project Apicula
Licensing	Gowin EDA Education edition is free without a licence for supported devices; the full edition needs a free licence requested from Gowin or a distributor at the time of writing
Updated	13 Nov 2026

Device families #

Family	Process	Logic	Positioning
GW1N / GW1NR / GW1NZ (LittleBee) R variants add in-package SDRAM or PSRAM, Z variants are ultra-low-power, NS variants add a Cortex-M3	55 nm	about 1k-9k LUTs	Small, cheap, low-power, with embedded flash
GW2A / GW2AR (Arora) GW2AR-18 with in-package SDRAM is on the Tang Nano 20K and Primer 20K	55 nm	18k-55k LUTs	Mid-sized with DSP and more block RAM
GW5A / GW5AT / GW5AST (Arora V) GW5AT adds SERDES up to 12.5 Gb/s, GW5AST adds a hard processor subsystem	22 nm	25k-138k LUTs	Current generation with SERDES, MIPI and hard processor options

Who they are

This page is for beginners who have bought or are considering a Tang board, and for engineers evaluating a low-cost alternative to Lattice or the small AMD parts. Gowin was founded in Guangzhou in 2014 and began shipping its 55 nm LittleBee devices soon after. The company’s early customers were in consumer electronics and display drivers, and it grew quickly in the Chinese market before gaining attention abroad through Sipeed’s Tang series boards, which put a Gowin FPGA, a USB programmer and a display connector on a board for the price of a lunch.

Gowin is now the most visible of the Chinese FPGA vendors outside China, and the only one with meaningful open-source toolchain support. The Chinese vendors page covers the others.

Toolchain

You install Gowin EDA, which runs on 64-bit Windows and Linux. The download is under 1 GB. There are two editions. The Education edition needs no licence and supports the devices on the common Tang boards, including GW1N, GW2A and some GW5A parts. The full edition supports every device and needs a free licence file, which you request from Gowin’s website or a distributor and which is tied to a MAC address. Synthesis is GowinSynthesis, with an option to use Synplify Pro if you have one. There is a built-in logic analyser and a programmer that talks to the FTDI or BL702 interfaces on Sipeed boards. There is no bundled simulator, so you use Icarus, Verilator or ModelSim with Gowin’s simulation libraries.

The open-source path is Project Apicula, which documents the bitstream format and plugs into Yosys and the himbaechel architecture of nextpnr. It covers GW1N, GW1NR, GW1NZ, GW1NS and GW2A devices well, including the PLL, block RAM and the in-package memory interfaces on the R parts, and GW5A support is in progress at the time of writing. openFPGALoader programs the Tang boards directly. See the open-source ecosystem page.

Pain points: the documentation is translated and sometimes thin, the timing analyser is basic, and licence requests through some distributors can take days.

Boards to start with

The Tang Nano 9K (GW1NR-9) is the cheapest board that is large enough for real work, with HDMI and a PSRAM in the package.
The Tang Nano 20K (GW2AR-18) adds 64 Mb of SDRAM in package and is popular for retro-computing cores.
The Tang Primer 20K is the same device as a module on a carrier with more I/O.
The Tang Mega 138K (GW5AST-138) is the route into Arora V with SERDES and PCIe.

Migration notes

Coming from AMD or Altera, constraints are split into a .cst physical file (IO_LOC and IO_PORT statements for pins and standards) and a .sdc timing file with the usual commands. Gowin EDA checks the SDC less strictly than Vivado or Quartus, so a missing clock constraint produces a warning rather than a failure, and you should read the timing report rather than trust a green build.

Primitives have Gowin names: rPLL and PLLVR for clocks, OSC for the internal oscillator, BUFG for global clocks, and SP, DP and SDP for single-port, dual-port and semi-dual-port block RAM. Most are generated through the IP Core Generator and instantiated as modules. Inference of block RAM and DSP works for standard templates. The logic cell is a 4-input LUT with a register, so a 9K part holds about half the logic of an AMD part with the same LUT count.

The GW1NR and GW2AR in-package memory is accessed through dedicated primitives and the pins are internal, which removes the usual PCB work but means a Gowin-specific controller.

Watch for

The Education edition device list changes between releases, so check that your part is covered. Gowin EDA on Linux requires a licence file even for the Education edition in some versions. Documentation for the GW5A family is newer and gaps are common. Sipeed boards use a mix of USB bridge chips, and the BL702-based ones need a specific openFPGALoader cable setting. Gowin is a Chinese company, and some customers in regulated industries need to consider procurement rules before designing a part in, which is outside the scope of this site. Parts are cheap but supply through Western distributors is thinner than for Lattice.