FPGA Guide
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Low-power and small FPGAs

The small FPGA families from Lattice, Efinix, Gowin, Renesas and Microchip, where their power goes, how sleep and clock gating help, and how to estimate consumption before you build.

Updated 13 Nov 2026 · iCE40 UltraPlus, CrossLink-NX, Trion, GW1N, ForgeFPGA, static power, dynamic power, sleep mode

Overview

Most FPGA writing is about the large parts, but most FPGAs sold are small. A 1,000 to 20,000 LUT device costing one to ten USD sits in cameras, wearables, industrial sensors and glue-logic roles, often running from a battery or a tight thermal budget. This hub is for engineers choosing and using those devices, where the question is rarely “will it fit” and usually “what does it draw”. The arithmetic of power on an FPGA is different enough from a microcontroller that it is worth learning properly.

An FPGA draws more than an ASIC doing the same job, because the routing multiplexers and configuration memory add capacitance and leakage. The small families fight that with older, lower-leakage processes (40 nm and 28 nm rather than 7 nm), flash or OTP configuration that needs no external memory, and fine-grained sleep modes. The result, on the best parts, is tens of microwatts standing by and a few milliwatts doing useful work.

Key ideas

Static versus dynamic power

Static power is what the device draws configured and idle. It comes from transistor leakage and is set by process, temperature and die size. It roughly doubles for every 10 to 15 degrees of junction temperature on older processes. Dynamic power is proportional to capacitance, the square of the supply voltage and the rate of switching, summed over every net. On an FPGA the routing dominates, so a design’s dynamic power depends on how many long wires toggle and how often, not on LUT count. The practical consequences: lower the core voltage where the part allows it, keep high-toggle logic physically compact, and clock-enable or clock-gate everything that is not needed each cycle. Block RAM and SerDes have their own fixed costs. A single enabled block RAM can draw more than a hundred LUTs.

Static (idle, configured)core leakageprocess, temperatureI/O bank biasstandards, terminationsconfig memorySRAM vs flash/OTPDynamic (switching)clock treetoggles every cycleroutinglargest sharelogic, RAM, DSPactivity x capacitanceleverslower Vcore, cooler boardsleep / power-down pinsclock enables, gated PLLslower clock, wider datacompact placementfewer I/O standardsRule of thumb for a 40 nm small FPGA: static tens to hundreds of microwatts, dynamic roughly 50 to 150 microwatts per MHzper thousand active LUTs. Measure on the development board, because activity factors vary wildly by design.
Where the milliwatts go in a small FPGA, and the levers that reduce each part

Sleep modes and wake-up time

The battery-friendly parts offer more than clock stopping. iCE40 UltraPlus has a low-power mode under 100 microwatts with state retained, and its hard SPI and I2C blocks can wake the fabric on a message. CrossLink-NX and Certus-NX have programmable power-down of unused banks. Gowin GW1N parts with embedded flash can hold configuration with power removed entirely and reconfigure in milliseconds. Renesas ForgeFPGA, the smallest of the lot at a few hundred to a few thousand LUTs, targets standby in the microampere range and is sold as a replacement for a handful of discrete logic parts. The variable to check is wake-up latency. An SRAM part that reloads from external flash needs tens of milliseconds and a burst of current, while a flash-based part is live in microseconds. For a duty-cycled sensor node, the reconfiguration energy per wake can exceed the work.

Estimating before you build

Every vendor ships a spreadsheet or tool that takes LUT count, clock frequency, an activity factor and the I/O list and returns a milliwatt figure. Lattice has Power Calculator inside Radiant, Efinix has the Efinity Power Estimator, Microchip has the PolarFire power estimator, and AMD and Altera have the Power Design Manager and Early Power Estimator for their larger parts. All of them are only as good as the activity factor you type in, and 12.5 percent (the usual default) is wrong for most designs. The reliable method is to run a gate-level simulation of a representative workload, export the switching activity (SAIF or VCD), and feed that to the vendor’s post-route analyser. Then measure. Development boards from Lattice and Efinix bring the core rail out to a jumper for exactly this purpose.

Where to start

Small FPGAs are the natural place to learn, and the beginner track runs on them. /learn/beginner/01-what-is-an-fpga/ explains why an FPGA draws what it draws, /learn/beginner/04-registers-clocks-and-state/ introduces clock enables, which are the first power tool, and /learn/beginner/08-counters-timers-and-debouncing/ is a good first design to measure. Try the same blinking design at 1 MHz and 48 MHz on an iCE40 board with an ammeter on the core rail and the difference will teach you more than the datasheet. An intermediate track on power-aware design is coming.

Tools and vendors

Family Vendor Process Logic range Configuration Positioning
iCE40 UltraPlus Lattice 40 nm 2.8k to 5.3k LUTs SRAM, external or NVCM Always-on sensing, open-source flow
CrossLink-NX, Certus-NX Lattice 28 nm FD-SOI 17k to 40k LUTs SRAM, fast boot MIPI bridging, low leakage
Trion Efinix 40 nm 4k to 120k LEs SRAM, external flash Small packages, cheap, hard MIPI on larger parts
Titanium Efinix 16 nm 35k to 1M LEs SRAM Higher performance at low power
GW1N, GW1NR Gowin 55 nm 1k to 9k LUTs Embedded flash plus SRAM Cheapest, in-package PSRAM on R variants
GW2A, GW5A Gowin 55 nm, 22 nm 18k to 138k LUTs SRAM Mid-range, Apicula support growing
ForgeFPGA Renesas not published hundreds to a few thousand LUTs OTP Discrete-logic replacement, free Go Configure tool
IGLOO2, PolarFire Microchip 65 nm, 28 nm 6k to 481k LEs Flash, live at power-up Lowest static power in the mid-range, security, reliability

Microchip claims PolarFire draws roughly half the static power of SRAM-based competitors at the same size, which is plausible given the flash configuration and the process, but compare your own numbers on the estimators.

Common mistakes

  • Reading the datasheet’s typical static figure at 25 degrees and designing for an enclosure at 70.
  • Forgetting the configuration flash, the regulators and the oscillator. On a small design these can draw more than the FPGA.
  • Using a free-running 100 MHz clock for a design that processes a sample every millisecond. Run slow, or run fast in bursts and sleep.
  • Leaving unused I/O banks powered and unused inputs floating.
  • Picking an SRAM-based part for a duty-cycled application without costing the reconfiguration energy.
  • Trusting the estimator’s default activity factor.

Going deeper