Wireless and SDR

Overview

A software-defined radio moves as much of the signal chain as possible from analogue hardware into digital processing. Between the antenna and the software there is still a stretch of signal at hundreds of megasamples per second where no processor can keep up, and that stretch is where the FPGA lives. This hub is for engineers building radios, test equipment, radar or spectrum sensing, and for DSP engineers who want to understand what changes when the signal is a carrier.

The field has two poles. At one end is the research and hobby SDR, where a USRP or similar front end streams samples to a host running GNU Radio and the FPGA does only decimation and framing. At the other end is the 5G radio unit, where an RFSoC digitises the band directly and the FPGA runs the entire physical layer. Most commercial work sits between them, and the skill is deciding which blocks earn their place in hardware.

Key ideas

Direct RF sampling and the digital front end

AMD’s Zynq UltraScale+ RFSoC integrates ADCs and DACs that sample at several gigasamples per second on the same die as the MPSoC and the fabric. With a converter that fast, a signal at 2 GHz or 4 GHz can be sampled directly, without an analogue mixer, and the down-conversion to baseband happens in a digital mixer driven by an NCO. The RF data converter block includes those mixers and a chain of decimation filters, so the fabric receives a complex baseband stream at a manageable rate. The third generation, and the Zynq RFSoC DFE parts, add hardened digital front end blocks: digital up and down conversion, crest factor reduction and digital pre-distortion, which are the standard radio unit functions that would otherwise eat most of the fabric. Altera and others offer similar integrations through JESD204 links to external converters rather than on-die converters, and that path is also how most non-AMD designs work.

OFDM pipelines

OFDM, used by Wi-Fi, LTE and 5G NR, splits a wide channel into many narrow sub-carriers and modulates them together with an inverse FFT. The receive pipeline is a sequence of fixed-function blocks: timing and frequency synchronisation, cyclic prefix removal, an FFT, channel estimation from known pilot symbols, equalisation, demapping of each sub-carrier to soft bits, and then decoding. Each block is a well-understood DSP structure, so an OFDM receiver is a good fit for a streaming FPGA design built from the pieces described under /topics/dsp/. The variable parts (bandwidth, sub-carrier spacing, numerology in 5G terms) make parameterisation the main design challenge.

Channel coding: LDPC and polar

5G NR uses LDPC codes for data and polar codes for control channels. An LDPC decoder passes messages between check nodes and variable nodes for a number of iterations, and the quasi-cyclic structure of the 5G codes maps onto an FPGA as rows of parallel processing units and a barrel-shifting memory. Throughput scales with parallelism, and a gigabit-per-second decoder is several hundred thousand LUTs or a hard block. AMD provides a soft-decision FEC hard block on some RFSoC parts for exactly this reason. Polar decoders use successive cancellation list decoding, which is more sequential and more awkward in hardware. Writing either decoder from scratch is a serious project. Vendor IP, commercial IP and a few open-source implementations exist.

SDR frameworks and FPGA offload

GNU Radio is the standard open-source framework for building a signal chain in software from blocks. The USRP family from Ettus Research (part of NI) is the common front end, and its FPGA runs the decimation, interpolation and framing, with RFNoC providing a framework for putting your own blocks on the USRP’s FPGA and connecting them into a GNU Radio flowgraph. Other hardware ranges from inexpensive receivers with no FPGA at all, through the ADALM-Pluto and LimeSDR with a small FPGA, to full RFSoC boards. The decision is always the same: keep the fast, fixed, high-rate processing in the FPGA and move the slow, flexible, low-rate processing to the host. Latency-sensitive loops, such as a MAC that must respond in microseconds, also belong in hardware.

Where to start

• /learn/beginner/04-registers-clocks-and-state/ and /learn/beginner/09-memories-block-ram-and-fifos/ cover the pipelines and buffers every receive chain needs.
• The DSP hub at /topics/dsp/ covers the arithmetic, NCOs, CIC filters and FFTs that this hub assumes.
• The SoC hub at /topics/soc-fpgas/ explains the processor side of an RFSoC.

Intermediate lessons on an NCO and digital mixer, an OFDM symbol synchroniser and a first RFSoC loopback are coming.

Tools and vendors

Converter resolutions and sample rates vary by part. Check the datasheet for the specific RFSoC generation.

Common mistakes

• Sampling a signal directly without checking which Nyquist zone it lands in and whether the anti-alias filter matches.
• Running the whole chain at the converter rate instead of decimating as early as possible.
• Ignoring converter clock jitter, which sets the noise floor at high input frequencies more than the ADC’s resolution does.
• Underestimating a channel decoder. An LDPC decoder is a project, not a block.
• Streaming raw samples to the host over an interface that cannot carry them, then blaming the software.
• Forgetting that a radio must be legal to transmit. Test into a dummy load or a shielded box.

Going deeper

• AMD DS889, Zynq UltraScale+ RFSoC Data Sheet: Overview: converter counts and rates per part.
• AMD PG269, Zynq UltraScale+ RFSoC RF Data Converter: the mixer, decimation and configuration interface of the converter block.
• 3GPP TS 38.212, NR Multiplexing and channel coding: the LDPC and polar code definitions.
• GNU Radio documentation: the framework, tutorials and block reference.
• Ettus UHD and RFNoC manual: the USRP driver and the FPGA block framework.
• Harris, Multirate Signal Processing for Communication Systems: the digital front end arithmetic behind every chain above.