Lattice and NXP pair Nexus FPGAs with the i.MX 95 over PCIe for industrial edge designs

Lattice Semiconductor announced the Lattice NXP PCIe Companion solution on 10 November 2026. It is a reference design rather than a new device. It connects a Lattice Nexus FPGA to NXP’s i.MX 95 applications processor over PCIe, with the Certus-NX and the larger CertusPro-NX as the FPGA options. The processor handles vision, graphics and application code, while the FPGA provides low-latency, deterministic I/O and whatever custom interfaces an industrial system needs. Lattice also pitches it as a way to modernise older designs that need newer interface standards.

The two companies describe the result as supporting the EU Cyber Resilience Act and CNSA 2.0 requirements, with hardware-rooted security on both chips. NXP’s quoted executive credits the i.MX 95 with post-quantum cryptography support. The design is available now in discrete, system-on-module and multi-chip-module configurations. Lattice supplies the FPGA reference design and its development tools, NXP provides the software driver and documentation, and reference designs and evaluation kits can be obtained through Arrow Electronics. The release does not state which PCIe generation or lane count is used, nor any throughput figures, so those details will have to come from the design files themselves.

Why it matters

An FPGA as a PCIe companion to an applications processor is a well-worn pattern. What is new is a joint, vendor-supported starting point with drivers already written for both ends, which removes the slowest part of such projects. Certus-NX is a mid-size, low-power device with hard PCIe, so the FPGA side builds in Radiant. Before adopting it, check how the driver exposes FPGA registers to Linux user space, and whether the security claims cover the FPGA bitstream as well as the processor’s secure boot.