QuickLogic

Device families #

Who they are

This page is for engineers interested in embedded FPGA (eFPGA) IP, in very low-power sensor processing, or in a vendor that treats the open-source toolchain as its primary flow. QuickLogic was founded in 1988 and spent its first decades on antifuse FPGAs for military and industrial customers, then on low-power consumer bridging devices. Around 2019 it changed direction towards licensing eFPGA IP, which lets a chip designer place a block of programmable logic inside an ASIC, and towards the EOS S3, a microcontroller with a Cortex-M4F and a small fabric aimed at always-on sensor tasks.

In 2020 QuickLogic became the first vendor to make an open-source flow its official development tool, contributing bitstream documentation to SymbiFlow (now F4PGA). It remains a small company, but one worth knowing about if your interest is eFPGA or open tools.

Toolchain

For the EOS S3 you install the QORC SDK, a GitHub repository with the Zephyr and FreeRTOS board support, the flash programmer and example applications. The FPGA flow is Aurora, QuickLogic’s packaging of Yosys for synthesis and VPR (from the VTR project) for place and route, with the F4PGA architecture files for the S3 fabric. Everything is free and runs on Linux, with a Windows installer available. There is no proprietary synthesis, no licence server and no registration.

For eFPGA IP, the Australis generator produces the IP and the matching toolchain for a chosen foundry node, cell library and fabric size. That is a commercial engagement rather than a download.

Pain points: VPR is a research tool and its runtime and quality of results trail commercial tools. The S3 fabric is small, so you cannot build much more than a sensor pre-processor or a custom peripheral in it. Vendor documentation is spread across GitHub readmes and a few application notes.

Boards to start with

• The QuickFeather is the open-hardware Feather-format board with an EOS S3, a microphone, an accelerometer and a pressure sensor, designed for tinyML experiments.

SparkFun sold a Thing Plus board with the same device, and SensiML offers a kit for its machine-learning workflow, but at the time of writing the QuickFeather is the one to look for. There are no public boards for the PolarPro 3 line.

Migration notes

Coming from AMD or Altera, forget most of what you know about vendor project files. A design is a Verilog file, a .pcf pin constraint file and a command line or a Makefile. Synthesis is Yosys, so the supported Verilog subset is what Yosys supports, which is most of Verilog-2005 and a useful part of SystemVerilog. VHDL requires the GHDL plugin for Yosys.

The S3 fabric has 4-input LUTs grouped into logic cells, a few 8 kbit RAM blocks and two multipliers. There are no PLLs in the fabric: clocks come from the MCU’s clock tree and are handed to the fabric through a fixed interface. The fabric talks to the Cortex-M4F through an AHB-Lite wishbone-style bridge and the register map is documented in the technical reference manual. Timing analysis in VPR is functional but basic, with a single target frequency rather than a full SDC.

If you are evaluating eFPGA IP, the comparison is not with a discrete FPGA but with Achronix Speedcore, Flex Logix EFLX and Menta eFPGA. See the eFPGA topic page.

Watch for

QuickLogic is a small public company and its priorities have shifted several times, so the EOS S3 may not see a successor. The open-source flow is a strength for transparency but a weakness for quality of results, and there is no commercial flow to fall back on. The S3 fabric is tiny by any modern standard and a beginner expecting to run a soft processor in it will be disappointed. Stock of the QuickFeather and Thing Plus has been intermittent. eFPGA IP evaluation requires a non-disclosure agreement and a real project, so hobbyists cannot explore Australis.